Dillon Engineering
  • Home
  • Company
    • About Us
    • Contact Us
    • Jobs
  • Services
    • Applications
    • Markets
    • Why Hire DE? >
      • Top Down Meets Bottom Up
    • When to Hire DE?
  • FFT IP
    • Load Unload FFT
    • UltraLong FFT >
      • UltraLong FFT IP Core for Xilinx FPGAs
    • Parallel FFT
    • Dual Parallel FFT
    • Parallel Butterfly FFT
    • Mixed Radix FFT >
      • Mixed Radix FFT IP Core for Xilinx FPGAs
    • Pipelined FFT >
      • FFT_PIPE IP Core for Xilinx FPGAs
    • 2D FFT
    • Other IP Cores >
      • Floating Point IP >
        • FPLIC Riviera Evaluation
        • FPLIC Download
        • FPLIC ParaCore Parameters
      • AES Crypto IP >
        • AES PatraCore Parameters
        • AES Background Information
    • FFT/IFFT ParaCore Parameters
  • Ingenuity
    • ParaCore Architect IP Generation >
      • PCA Flow
      • PCA Example
    • Modeling
    • Verification
    • Fixed vs. Floating Point
    • Fixed Point Math
  • News
    • DE Releases Mixed Radix FFT IP Cores for Xilinx FPGAs
    • DE Release UltraLong FFT IP Cores for Xilinx FPGAs
    • DE Releases FFT_PIPE IP Cores for Xilinx FPGAs
    • Floating Point Modules Evaluation Available
    • Chip Design Magazine Article
    • BCD Math
    • UltraLong FFT IP Success
    • DE Releases FFT IP Cores
  • Docs
    • HowTo >
      • Power Calculation Using XPower
      • Strings in Verilog
      • Inferring Block RAM vs. Distributed RAM in XST and Precision
      • Verilog RTL Coding Style Guidelines, Tips and Template
    • Downloads >
      • gen_ise-sh
      • gen-ise-sh-py
      • deModel
      • deModel_tar_gz
      • deModel_win32_exe
    • HPEC Presentations >
      • HPEC 2003 Presentation
      • HPEC 2004 Presentation
      • HPEC 2007 Abstract
      • HPEC 2007 Posters
    • FFT >
      • Load Unload FFT IP Datasheet
      • FFT_MIXED Candidate Core Datasheet
      • DE FFT IP and Sundance SMT702 Flyer
      • UltraLong FFT IP Core for Xilinx Datasheet
      • PIPE_FFT for Xilinx FPGAs Datasheet
      • FFT Datasheet
      • Floating Point FFT Factsheet
      • FFT Success
    • Sundance DE Partnership Release
    • FPGA Webcast
    • FPGAs Go, Go, Go
    • AES Datasheet
    • FPLIC Specification
    • DE Overview

Parallel Butterfly FFT


Parallel butterfly structure for multiple point (rank-at-a-time) processing performance

The Parallel Butterfly FFT IP Core provides efficient continuous data FFT calculations at the rate of multiple points per clock cycle. A bank of parallel butterflies executes the FFT one rank at a time on multiple I/O streams.

Block Diagram

Block diagram of the Parallel Butterfly FFT:
Picture

Key Features

  • ParaCore Architect parametric-based core provides maximum adaptability and flexibility (see details on the FFT Parameters)
  • Completely proven in many real-world applications
  • Supports any radix-2 length FFT and IFFT transformations
  • Variable length option for runtime per-transform length select
  • Fixed- or floating-point complex I/O of any width
  • Integrated Hanning Window (user defined)
  • Optional magnitude output
  • Designed for continuous transformations with extremely fast conversion times
  • Naturally ordered I/O streams
  • Parallel I/O paths for maximum throughput
  • Massively parallel butterfly architecture, from 1 butterfly up to the full logic capacity of the target device.
  • Available in generic HDL or targeted EDIF formats
  • Delivered as a completely self contained module with a full testbench

Additional Information

Our FFT core is based on radix-2 reduction, which results in a very efficient implementation capable of any power-of-2 length FFT or IFFT (see also our FFT Datasheet or our Floating Point FFT Factsheet).

A sample of the FFT ParaCore parameters used to build the DE FFT IP Core.

Please feel free to contact us with any FFT core questions or comments.

Device Fit Estimate or Additional Information

Fill out the FFT IP Fit/Information Form to obtain a device usage estimate in your target technology or to obtain additional information about a specific FFT architecture.
OUR SERVICES

Applications
Markets

OUR IP

FFT
AES
Floating Point

CONTACT US

info@dilloneng.com
952.836.2413
Contact Page
Picture

© 2022 Dillon Logic LLC
All Rights Reserved