Fixed Point Math
In an FPGA or ASIC design, comprehensive fixed point arithmetic techniques make the difference in fidelity.
Overview
When converting all or portions of a floating point algorithm to fixed point FPGA or ASIC implementation, a deep understanding of fixed point arithmetic issues and effects is necessary to achieve optimal fidelity in the data outputs. This article provides an overview of the primary factors, and outlines some key details about the infrastructure that we at Dillon Engineering have developed to make painless fixed point conversions.
At the core of most DSP algorithms are, quite simply put, a lot of multiplies and adds of different data types. FFTs, filters, correlations, interpolations, and related operations are built on data multiply/add stages that result in the basic fixed point artifact of bit-width growth. Compounding the issue, input and constant data come from sources of varying numeric types and must be combined. Here we look at the bottom-line issue of maintaining precision and overall data fidelity while using a reasonable amount of hardware resources, i.e. achieving the optimal fixed point implementation.
At the core of most DSP algorithms are, quite simply put, a lot of multiplies and adds of different data types. FFTs, filters, correlations, interpolations, and related operations are built on data multiply/add stages that result in the basic fixed point artifact of bit-width growth. Compounding the issue, input and constant data come from sources of varying numeric types and must be combined. Here we look at the bottom-line issue of maintaining precision and overall data fidelity while using a reasonable amount of hardware resources, i.e. achieving the optimal fixed point implementation.
Numeric Formats
As data is processed through the stages of an algorithm, a multitude of different numeric types may need to be supported. Whether ADC inputs, coefficients, feedback or intermediate data, an efficient design and modeling process must be able to seamlessly support any data combinations of:
- Real and complex
- Unsigned and signed
- Different signed formats including twos-complement, sign-and-magnitude, and ones-complement
- Integer, normalized, and mixed radix point
- Fixed point of different bit widths
- Single- and double-precision floating point
Scaling
Due to resource or performance limitations, most hardware systems cannot afford to carry all fixed point bit-width growth along to the output, and thus must scale at intermediate stages along the way. Whether at the output of low-level operations such as individual multipliers, or of larger building blocks such as FFT butterflies, effective scaling will result in hitting the sweet spot of dynamic range and precision. In a robust design environment, it is necessary to be able to quickly and easily determine at what stages to scale as well as what bit-widths to scale to, also handling the issues of rounding and overflow.
Rounding issues
When data is scaled, it must be decided how the remaining least significant bits of data should be handled. The simplest and lowest impact is to truncate (floor). The most intuitive is to round to nearest. Where effects of quantization error are a concern, round-to-even may be appropriate at the expense of additional logic. Effective rounding solutions should be able to incorporate any rounding scheme at any scaling stage independently, quickly and accurately.
Overflow issues
Also with scaling comes the potential for overflow beyond the result's most significant bit. Due to its drastic data impact, potential overflow conditions are usually guarded with a saturate at maximum value. However, it may be more desirable to carry overflow conditions along at intermediate stages via larger bit-widths and saturate only after other a group of math operations have completed. Properly scoped fixed point solutions should provide this flexibility.
Dillon Engineering Solutions
At Dillon Engineering, we have developed our fixed point conversion flow based on rapid modeling, closed-loop adjustments, and equivalent HDL implementation. Briefly described, we will start with an algorithm and system constraints such as data widths and hardware utilization bounds. We will then implement a model using derived or provided fixed point parameters, simulate using auto-generated or canned data sets, and analyze the performance results against requirements such as signal-to-noise ratio. Once the model is in place, further iterations with new parameters are usually trivial to implement. HDL is auto-generated from our IP creation tools or hand-coded where required, with resource and performance predictions available along the way from empirical data and synthesis results.
The following are advantages to using the Dillon Engineering flow:
The following are advantages to using the Dillon Engineering flow:
- Our model class libraries support fixed point of any width, floating point, and complex numeric formats
- Our model class libraries support robust scaling, rounding, and saturation options, and trap on overflows and other exceptions
- Our Python modeling takes advantage of the rich array processing and analysis capabilities of NumPy and links to graphical plotting capabilities comparable to expensive numerical analysis tools
- C modeling is incorporated where the simulation speed of compiled code is advantageous
- Our models are always lock-step designed and verified with our HDL
- Existing IP cores and HDL designs allow early hardware utilization prediction accuracy
- Our model data generation class libraries easily produce robust data sets or perform file I/O
Fixed Point Model Download
Visit deModel for more information and to download a fixed point math class for Python.
