Floating Point Library IP Core
The Dillon Engineering Floating Point Library IP Core is a set of parametric IEEE 754 compatible modules
Dillon Engineering’s Floating-Point Library IP Core has been developed using our state-of-the-art ParaCore Architect™ utility. The result is a highly parameterized core that can be quickly and easily tailored to meet the needs of any application. By means of ParaCore Architect, this core can also be quickly and easily re-targeted towards any FPGA or ASIC implementation technology.
The complexities of the floating-point library functions are controlled via compile time parameters (see also descriptions of these Functions and Parameters). The use of pipeline stages (for increased performance), the precision and size of the floating-point numbers, and many other parameters control the amount of logic used and the precision of the generated modules. This means that our floating-point library core modules use only as much logic as is required for a given application.
Since ParaCore Architect can be used to generate either VHDL or Verilog, the resulting floating-point library modules can be easily included into clients’ applications when the performance of floating-point math is required.
The complexities of the floating-point library functions are controlled via compile time parameters (see also descriptions of these Functions and Parameters). The use of pipeline stages (for increased performance), the precision and size of the floating-point numbers, and many other parameters control the amount of logic used and the precision of the generated modules. This means that our floating-point library core modules use only as much logic as is required for a given application.
Since ParaCore Architect can be used to generate either VHDL or Verilog, the resulting floating-point library modules can be easily included into clients’ applications when the performance of floating-point math is required.
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Device Fit Estimate
Fill out the FPLIC Module Fit Form to obtain a device usage estimate in your target technology. Additional Information and IEEE Compatibility
Additional Information and IEEE Compatiblity
The floating-point library core is fully compatible with IEEE 754 single and double precision math. However, support for IEEE 754 special cases is optional, thereby allowing the logic requirements to be reduced when the application doesn't require special-case tracking.
It should also be noted that not all applications require the use of full IEEE (single or double) precision data. Thus, the floating-point library core can also be configured to work with any required exponent and mantissa lengths by means of the appropriate ParaCore Parameters. (See also our Floating-Point Library Datasheet for more details on this IP core.)
Please feel free to contact us with any floating-point library core questions or comments.
For more detailed information refer to the FPLIC Datasheet.
It should also be noted that not all applications require the use of full IEEE (single or double) precision data. Thus, the floating-point library core can also be configured to work with any required exponent and mantissa lengths by means of the appropriate ParaCore Parameters. (See also our Floating-Point Library Datasheet for more details on this IP core.)
Please feel free to contact us with any floating-point library core questions or comments.
For more detailed information refer to the FPLIC Datasheet.
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