Dillon Engineering
  • Home
  • Company
    • About Us
    • Contact Us
    • Jobs
  • Services
    • Applications
    • Markets
    • Why Hire DE? >
      • Top Down Meets Bottom Up
    • When to Hire DE?
  • FFT IP
    • Load Unload FFT
    • UltraLong FFT >
      • UltraLong FFT IP Core for Xilinx FPGAs
    • Parallel FFT
    • Dual Parallel FFT
    • Parallel Butterfly FFT
    • Mixed Radix FFT >
      • Mixed Radix FFT IP Core for Xilinx FPGAs
    • Pipelined FFT >
      • FFT_PIPE IP Core for Xilinx FPGAs
    • 2D FFT
    • Other IP Cores >
      • Floating Point IP >
        • FPLIC Riviera Evaluation
        • FPLIC Download
        • FPLIC ParaCore Parameters
      • AES Crypto IP >
        • AES PatraCore Parameters
        • AES Background Information
    • FFT/IFFT ParaCore Parameters
  • Ingenuity
    • ParaCore Architect IP Generation >
      • PCA Flow
      • PCA Example
    • Modeling
    • Verification
    • Fixed vs. Floating Point
    • Fixed Point Math
  • News
    • DE Releases Mixed Radix FFT IP Cores for Xilinx FPGAs
    • DE Release UltraLong FFT IP Cores for Xilinx FPGAs
    • DE Releases FFT_PIPE IP Cores for Xilinx FPGAs
    • Floating Point Modules Evaluation Available
    • Chip Design Magazine Article
    • BCD Math
    • UltraLong FFT IP Success
    • DE Releases FFT IP Cores
  • Docs
    • HowTo >
      • Power Calculation Using XPower
      • Strings in Verilog
      • Inferring Block RAM vs. Distributed RAM in XST and Precision
      • Verilog RTL Coding Style Guidelines, Tips and Template
    • Downloads >
      • gen_ise-sh
      • gen-ise-sh-py
      • deModel
      • deModel_tar_gz
      • deModel_win32_exe
    • HPEC Presentations >
      • HPEC 2003 Presentation
      • HPEC 2004 Presentation
      • HPEC 2007 Abstract
      • HPEC 2007 Posters
    • FFT >
      • Load Unload FFT IP Datasheet
      • FFT_MIXED Candidate Core Datasheet
      • DE FFT IP and Sundance SMT702 Flyer
      • UltraLong FFT IP Core for Xilinx Datasheet
      • PIPE_FFT for Xilinx FPGAs Datasheet
      • FFT Datasheet
      • Floating Point FFT Factsheet
      • FFT Success
    • Sundance DE Partnership Release
    • FPGA Webcast
    • FPGAs Go, Go, Go
    • AES Datasheet
    • FPLIC Specification
    • DE Overview

gen_ise_sh


Download

gen_ise_sh.py
File Size: 13 kb
File Type: py
Download File


Documentation

The script gen_ise_sh.py will generate necessary files and folders to run a Xilinx ISE implementation from the command line. The advantage of this script is that all necessary configurations are done in this one file at one place. Running the script will then generate a Makefile which in turn calls all command line tools of ISE to run the implementation.

There are two requirements to use this script:

  • Python programming language
  • make, for example GNU make
All necessary configurations are done in the first section of the script, until a note further below marks the end of the parameter section.  Then just run the script with the command:
./gen_ise_sh.py

or

python gen_ise_sh.py

One result of the run will be a generated Makefile which will run all steps from synthesis to bitgen and create a .mcs file as well.


One result of the run will be a generated Makefile which will run all steps from synthesis to bitgen and create a .mcs file as well.

Generated files and folders are partly dependent on the specified variable 'topmodule'. In detail the generated files and folders are:

./Makefile
./<topmodule>.xst
./<topmodule>.prj
./<topmodule>.lso
./tmp/
./xst/
./xst/work

The script supports mixed language designs. Based on the file ending .v or .vhd it creates the respective entry in the .prj file for synthesis.

The script has been tested with ISE 6.3, 7.1, 8.1, and 9.1.

Usage:

- expect environment variable XILINX to be set
- adjust parameters and specify logic files to be included
- >python gen_ise_sh.py
- >make all

That's it.


OUR SERVICES

Applications
Markets

OUR IP

FFT
AES
Floating Point

CONTACT US

info@dilloneng.com
952.836.2413
Contact Page
Picture

© 2022 Dillon Logic LLC
All Rights Reserved