Dillon Engineering
  • Home
  • Company
    • About Us
    • Contact Us
    • Jobs
  • Services
    • Applications
    • Markets
    • Why Hire DE? >
      • Top Down Meets Bottom Up
    • When to Hire DE?
  • FFT IP
    • Load Unload FFT
    • UltraLong FFT >
      • UltraLong FFT IP Core for Xilinx FPGAs
    • Parallel FFT
    • Dual Parallel FFT
    • Parallel Butterfly FFT
    • Mixed Radix FFT >
      • Mixed Radix FFT IP Core for Xilinx FPGAs
    • Pipelined FFT >
      • FFT_PIPE IP Core for Xilinx FPGAs
    • 2D FFT
    • Other IP Cores >
      • Floating Point IP >
        • FPLIC Riviera Evaluation
        • FPLIC Download
        • FPLIC ParaCore Parameters
      • AES Crypto IP >
        • AES PatraCore Parameters
        • AES Background Information
    • FFT/IFFT ParaCore Parameters
  • Ingenuity
    • ParaCore Architect IP Generation >
      • PCA Flow
      • PCA Example
    • Modeling
    • Verification
    • Fixed vs. Floating Point
    • Fixed Point Math
  • News
    • DE Releases Mixed Radix FFT IP Cores for Xilinx FPGAs
    • DE Release UltraLong FFT IP Cores for Xilinx FPGAs
    • DE Releases FFT_PIPE IP Cores for Xilinx FPGAs
    • Floating Point Modules Evaluation Available
    • Chip Design Magazine Article
    • BCD Math
    • UltraLong FFT IP Success
    • DE Releases FFT IP Cores
  • Docs
    • HowTo >
      • Power Calculation Using XPower
      • Strings in Verilog
      • Inferring Block RAM vs. Distributed RAM in XST and Precision
      • Verilog RTL Coding Style Guidelines, Tips and Template
    • Downloads >
      • gen_ise-sh
      • gen-ise-sh-py
      • deModel
      • deModel_tar_gz
      • deModel_win32_exe
    • HPEC Presentations >
      • HPEC 2003 Presentation
      • HPEC 2004 Presentation
      • HPEC 2007 Abstract
      • HPEC 2007 Posters
    • FFT >
      • Load Unload FFT IP Datasheet
      • FFT_MIXED Candidate Core Datasheet
      • DE FFT IP and Sundance SMT702 Flyer
      • UltraLong FFT IP Core for Xilinx Datasheet
      • PIPE_FFT for Xilinx FPGAs Datasheet
      • FFT Datasheet
      • Floating Point FFT Factsheet
      • FFT Success
    • Sundance DE Partnership Release
    • FPGA Webcast
    • FPGAs Go, Go, Go
    • AES Datasheet
    • FPLIC Specification
    • DE Overview

Dillon Ingenuity 


At DE, advanced capabilities enable ingenious solutions.  One definition of ingenuity is "cleverness in design".  This implies doing things a little differently, such that the outcome is more proficiently and efficiently achieved.  Perhaps this is inventing something from scratch.  Or maybe just applying something existing in a way that hadn't been done before.

At Dillon Engineering, we have developed capabilities that go beyond the standard design flow.  In this age of larger logic devices, more complex applications, yet more tenuous design schedules, our expertise in higher-level code generation, modeling and verification makes the difference in productivity and precision.  When looking to engage a design team that truly gets it and knows how to get there from here better than the others, look no further than Dillon Engineering.

Visit the following for examples of Dillon ingenuity in action.

  • HDL auto-generation capabilities with our internally-developed ParaCore Architect tool.
  • High-level language modeling for fast and accurate algorithm representation.
  • Robust verification techniques for streamlined, comprehensive model and HDL simulation.
  • Fixed vs Floating Point for addressing the issues of floating point to fixed point conversion.
  • Fixed Point Math for detailing fixed point math formats and operations.
These pages discuss some of the steps taken in the following diagram on the DE design and verification flow:

Picture
OUR SERVICES

Applications
Markets

OUR IP

FFT
AES
Floating Point

CONTACT US

info@dilloneng.com
952.836.2413
Contact Page
Picture

© 2022 Dillon Logic LLC
All Rights Reserved