gen_ise_sh_py
File Contents
#!/usr/bin/python
#######################################################################
#
#
# COPYRIGHT (C) 2005-2013, DILLON ENGINEERING
# All rights reserved.
#
# Dillon Engineering http://www.dilloneng.com
# info@dilloneng.com 952-836-2413
#
# This software is provided by Dillon Engineering "as is".
#
# Redistributions of this software, with or without modification,
# must reproduce the above copyright notice, the address and contact
# information of Dillon Engineering, and this license statement.
#
# Dillon Engineering Inc. shall have no liability to any one,
# for damages caused by the use of this software.
#
# -------------------------------------------------------------------
#
# This script will generate necessary files and folders to run
# a Xilinx ISE implementation from the command line.
#
# There are two requirements to use this script:
# - Python programming language http://www.python.org
# - make, for example Gnu make http://www.gnu.org/software/make/
#
# All necessary configurations are done in the first section of the
# script until a note with the text 'end of defining parameters' further
# below. Then just run the script with the command:
#
# ./gen_ise_sh.py
#
# or
#
# python gen_ise_sh.py
#
# One result of the run is a generated Makefile which will run all steps
# from synthesis to bitgen and create a .mcs file as well.
#
# Generated files and folders are partly dependent on the specified
# variable 'topmodule'. In detail the generated files and folders are:
#
# ./Makefile
# ./<topmodule>.xst
# ./<topmodule>.prj
# ./<topmodule>.lso
# ./tmp/
# ./xst/
# ./xst/work
#
#
# The script supports mixed language designs. Based on the file ending
# .v or .vhd it creates the respective entry in the .prj file for synthesis.
#
# The script has been tested with ISE 6.3, 7.1, 8.1, and 9.1.
#
# Usage:
#
# - expect environment variable XILINX to bet set
# - adjust parameters and specify logic files to be included
# - >python gen_ise_sh.py
# - >make all
#
# That's it.
#
#
__revision__ = "$Rev: 419 $"
__data__ = "$Date: 2007-09-17 23:54:27 +0200 (Mon, 17 Sep 2007) $"
__version__ = "1.0"
import os, sys
#
# Define the parameters
#
src_extra = None
# files
# path to src_files and ucf_file
src_dir = './'
# src files, assumed in folder src_dir
# for verilog use .v for vhdl use .vhd
src_files = [ 'support.v', 'emulator_clock_synch.v', 'cd4046_pll.v', 'seg17_xil.v',
'ram_noisy.v', 'd264.v']
# ucf file, assumed in folder src_dir
ucf_file = 'd264.ucf'
# full path with each file, otherwise same as normal src_file
# if you don't need this option just comment it out
src_extra = ['../../coregen/internal_sram.v'] # full path needed
topmodule = 'd264'
# device information
device = 'xc3s5000'
speed = '5'
package = 'fg900'
# map options
map_opt = '-cm area -pr b -k 4 -c 100 -tx off'
# par options
par_opt = '-w -ol std -t 1'
# synthesis parameters
tmp_dir = 'tmp'
hdp_dir = 'xst'
syn_param = """
#
# Source parameters
#
-ifn %(topmodule)s.prj
-ifmt mixed
-iuc NO
#
# Target parameters
#
-ofn %(topmodule)s
-ofmt NGC
-p %(device)s-%(speed)s-%(package)s
#
# Source options
#
-top %(topmodule)s
-fsm_extract YES -fsm_encoding Auto
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-mux_extract YES
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-mult_style auto
-resource_sharing YES
# this option need a dir to be used
# -vlgincdir
-register_balancing No
#
# Target options
#
-iobuf YES
-max_fanout 100
-bufg 4
-register_duplication YES
-equivalent_register_removal YES
-slice_packing YES
-iob auto
#
# General options
#
-opt_mode Speed
-opt_level 1
-hierarchy_separator _
-bus_delimiter <>
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-write_timing_constraints NO
-case maintain
-slice_utilization_ratio 100
-slice_utilization_ratio_maxmargin 5
#
# Other options
#
-verilog2001 YES
-lso %(topmodule)s.lso
-read_cores YES
-cross_clock_analysis NO
-optimize_primitives NO
"""% locals()
# bitgenerator options
# depending on the device some options might not be usable. Check with
# ISE what can be used and what not.
bit_gen_g_options = []
bit_gen_g_options.append('DebugBitstream:No')
bit_gen_g_options.append('Binary:no')
bit_gen_g_options.append('CRC:Enable')
bit_gen_g_options.append('ConfigRate:6')
bit_gen_g_options.append('CclkPin:PullUp')
bit_gen_g_options.append('M0Pin:PullUp')
bit_gen_g_options.append('M1Pin:PullUp')
bit_gen_g_options.append('M2Pin:PullUp')
bit_gen_g_options.append('ProgPin:PullUp')
bit_gen_g_options.append('DonePin:PullUp')
bit_gen_g_options.append('TckPin:PullUp')
bit_gen_g_options.append('TdiPin:PullUp')
bit_gen_g_options.append('TdoPin:PullUp')
bit_gen_g_options.append('TmsPin:PullUp')
bit_gen_g_options.append('UnusedPin:PullDown')
bit_gen_g_options.append('UserID:0xFFFFFFFF')
bit_gen_g_options.append('DCMShutDown:Disable')
bit_gen_g_options.append('StartUpClk:CClk')
bit_gen_g_options.append('DONE_cycle:4')
bit_gen_g_options.append('GTS_cycle:5')
bit_gen_g_options.append('GWE_cycle:6')
bit_gen_g_options.append('LCK_cycle:NoWait')
bit_gen_g_options.append('Match_cycle:Auto')
bit_gen_g_options.append('Security:None')
bit_gen_g_options.append('DonePipe:No')
bit_gen_g_options.append('DriveDone:Yes')
#
# end of defining parameters
#
# You don't need to change anything beyond this, unless you want to
# improve the script.
#
# If you do so, we would love to hear from you. Send us your
# improvements to info@dilloneng.com
#######################################################################
def construct_makefile():
head = ['#']
head.append("# This file was created by the script '%s'"% sys.argv[0])
head.append("# Change parameters in that script, not in this Makefile")
head.append('#')
# Variables in the Makefile
var = ['#']
var.append('TOP=%s'% topmodule)
var.append('PART=%(device)s-%(package)s-%(speed)s'% globals())
var.append('MAP_OPTS=%s'% map_opt)
var.append('PAR_OPTS=%s'% par_opt)
var.append('#\n#\n#')
var.append('SRCDIR=%(src_dir)s'%globals())
var.append('UCF=%s' % os.path.join(src_dir, ucf_file))
# add files
file_str = 'SRC_FILES= '
first = True
for file in src_files :
if not first :
file_str += ' '
file_str += os.path.join(src_dir, file)
first = False
if(src_extra):
for file in src_extra:
if not first :
file_str += ' '
file_str += '%s'%(file)
first = False
var.append(file_str)
var.append("#")
var.append("SYN =%s"% os.path.join(xil_path, "xst"))
var.append("NGDBUILD =%s"% os.path.join(xil_path, "ngdbuild"))
var.append("MAP =%s"% os.path.join(xil_path, "map"))
var.append("PAR =%s"% os.path.join(xil_path, "par"))
var.append("BITGEN =%s"% os.path.join(xil_path, "bitgen"))
var.append("TRCE =%s"% os.path.join(xil_path, "trce"))
var.append("REPORTGEN =%s"% os.path.join(xil_path, "reportgen"))
var.append("PROMGEN =%s"% os.path.join(xil_path, "promgen"))
var.append("NETGEN =%s"% os.path.join(xil_path, "netgen"))
var.append("#")
try :
var.append('export XILINX=%(xilinx)s'% globals())
except:
pass
var.append('export LD_LIBRARY_PATH=%(xil_path)s'% globals())
var.append('#')
var.append('BITGEN_OPTS = -w \\')
for i in range(len(bit_gen_g_options)-1):
var.append(' -g %s \\'%bit_gen_g_options[i])
var.append(' -g %s'%bit_gen_g_options.pop())
var.append('#\n#\n#\n#')
mfL = head + var
# default
mfL.append('default:')
mfL.append('\t@echo usage:')
mfL.append('\t@echo "\tmake all - builds all targets"')
mfL.append('\t@echo "\tmake reports - runs P&R and generates reports"')
mfL.append('\t@echo "\tmake verilog_sim - runs P&R and gererates verilog gatesim file"')
mfL.append('\t@echo "\tmake vhdl_sim - runs P&R and gererates VHDL gatesim file"')
mfL.append('\t@echo "\tmake bits - runs P&R and gererates bit file"')
mfL.append('\t@echo "\tmake prom - runs P&R and gererates prom file"')
mfL.append('#\n#')
# all
mfL.append('all: reports prom bits vhdl_sim verilog_sim')
mfL.append('#\n#')
# reports
mfL.append('reports: $(TOP)_par.dly $(TOP)_par.twr')
mfL.append('#\n#')
# verilog_sim
mfL.append('verilog_sim: $(TOP)_par.v')
mfL.append('#\n#')
# bits
mfL.append('bits: $(TOP).bit')
mfL.append('#\n#')
# prom
mfL.append('prom: $(TOP).mcs')
mfL.append('#\n#')
# vhdl_sim
mfL.append('vhdl_sim: $(TOP)_par.vhd')
mfL.append('#\n#')
# sim verilog
mfL.append('$(TOP)_par.v: $(TOP)_par.ncd')
mfL.append('\t$(NETGEN) -sim -ofmt verilog -w -s %s $(TOP)_par.ncd'%speed)
mfL.append('#\n#')
# sim vhdl
mfL.append('$(TOP)_par.vhd: $(TOP)_par.ncd')
mfL.append('\t$(NETGEN) -sim -ofmt vhdl -rpw 100 -w -s %s $(TOP)_par.ncd'%speed)
mfL.append('#\n#')
# MCS
mfL.append('$(TOP).mcs: $(TOP).bit')
mfL.append('\t$(PROMGEN) -w -p mcs -o $(TOP).mcs -u 0 $(TOP).bit')
mfL.append('#\n#')
# Report Delay
mfL.append('$(TOP)_par.dly: $(TOP)_par.ncd')
mfL.append('\t$(REPORTGEN) -delay -o $(TOP)_par $(TOP)_par.ncd')
mfL.append('#\n#')
# Report Timine
mfL.append('$(TOP)_par.twr: $(TOP)_par.ncd')
mfL.append('\t$(TRCE) $(TOP)_par $(TOP).pcf -u 10 -v 10 -o $(TOP)_par')
mfL.append('#\n#')
# Bitgen
mfL.append('$(TOP).bit: $(TOP)_par.ncd')
mfL.append('\t$(BITGEN) $(TOP)_par.ncd $(TOP).bit $(BITGEN_OPTS)')
mfL.append('#\n#')
# Plac & Route
mfL.append('$(TOP)_par.ncd: $(TOP)_map.ncd')
mfL.append('\t$(PAR) $(PAR_OPTS) $(TOP)_map.ncd $(TOP)_par.ncd $(TOP).pcf')
mfL.append('#\n#')
# Map
mfL.append('$(TOP)_map.ncd: $(TOP).ngd')
mfL.append('\t$(MAP) -p $(PART) $(MAP_OPTS) -o $(TOP)_map.ncd $(TOP).ngd $(TOP).pcf')
mfL.append('#\n#')
# Translate
mfL.append('$(TOP).ngd: $(TOP).ngc $(UCF)')
mfL.append('\t$(NGDBUILD) -dd tmp -aul -uc $(UCF) -p $(PART) $(TOP).ngc $(TOP).ngd')
mfL.append('#\n#')
# Synthesis
mfL.append('$(TOP).ngc: $(SRC_FILES)')
mfL.append('\t$(SYN) -ifn $(TOP).xst -ofn $(TOP)_xst_log.syr')
mfL.append('#\n#')
# very_clean
mfL.append("very_clean:")
mfL.append("\trm -fr %s" % tmp_dir)
mfL.append("\trm -fr %s" % hdp_dir)
mfL.append("\trm -f $(TOP)*")
mfL.append("\trm -f *.log")
mfL.append('#\n#')
# all_clean
mfL.append('all_clean:')
mfL.append('\trm -f $(TOP)*.ncd $(TOP)*.ngd $(TOP)*.ngo $(TOP)*.ngc')
mfL.append('#\n#')
# clean
mfL.append('clean:')
mfL.append('\trm -f $(TOP)*.ncd $(TOP)*.ngd $(TOP)*.ngo')
mfL.append('#\n#')
mf = '\n'.join(mfL)
return mf
#######################################################################
#
# main
#
if __name__ == '__main__':
if(not os.environ.get('XILINX')):
raise "ERROR: 'XILINX' environment variable needs to the be set!"
# Assuming the $XILINX variable is set accordingly
# need to differentiate xilinx map from unix map
host_type = os.environ.get('HOSTTYPE')
if(host_type == 'x86_64'):
xil_path = '${XILINX}/bin/lin64'
else:
xil_path = '${XILINX}/bin/lin'
# ... if not, add this
#xilinx = '/opt/xilinx'
print '\n\n-------------------------------------------------------------------------'
print 'Start generation of files and folders for ISE shell call'
# test for existence of necessary folders, if not, create them
if(not os.path.exists(tmp_dir)):
os.mkdir(tmp_dir)
print 'Created %(tmp_dir)s folder.' % locals()
if(not os.path.exists(hdp_dir)):
os.mkdir(hdp_dir)
print 'Created %(hdp_dir)s folder.' % locals()
if(not os.path.exists('%s/work'%hdp_dir)):
os.mkdir('%s/work'%hdp_dir)
print 'Created %(hdp_dir)s/work' % locals()
if(not os.path.exists(src_dir)):
raise "ERROR: The specified src_dir='%s' does not exists!" % src_dir
# Write .prj file
prj_file = open("%s.prj"%topmodule, mode='w')
for file in src_files:
v = file.find('.v')
vhdl = file.find('.vhd')
# verilog file
if((v > -1) and (vhdl < 0)):
line = "verilog work %s\n" % os.path.join(src_dir, file)
# vhdl file
elif((v > -1) and (vhdl > -1)):
line = "vhdl work %s\n" % os.path.join(src_dir, file)
prj_file.write(line)
# only add src_extra if it exists
if(src_extra):
for file in src_extra:
v = file.find('.v')
vhdl = file.find('.vhd')
# verilog file
if((v > -1) and (vhdl < 0)):
line = "verilog work %(file)s\n"% locals()
# vhdl file
elif((v > -1) and (vhdl > -1)):
line = "vhdl work %(file)s\n"% locals()
prj_file.write(line)
prj_file.close()
print 'Wrote the project file %s.prj'% topmodule
# Write .lso file
lso_file = open("%s.lso"%topmodule, mode='w')
lso_file.write('work')
lso_file.close()
print 'Wrote the lso file %s.lso'% topmodule
# Write .xst file
xst_id = open("%s.xst"%topmodule, mode='w')
xst_id.write("set -tmpdir %s\n"% tmp_dir)
xst_id.write("set -xsthdpdir %s\n"% hdp_dir)
xst_id.write("run")
xst_id.write(syn_param)
xst_id.close()
print 'Wrote the xst file %s.xst'% topmodule
# Write the Makefile
makefile_id = open("Makefile", mode='w')
makefile_id.write(construct_makefile())
makefile_id.close()
print 'Wrote the Makefile'
print '\nFinished!'
print "Type 'make all' to start the implementation"
