Dillon Engineering
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    • Why Hire DE? >
      • Top Down Meets Bottom Up
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  • FFT IP
    • Load Unload FFT
    • UltraLong FFT >
      • UltraLong FFT IP Core for Xilinx FPGAs
    • Parallel FFT
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    • Mixed Radix FFT >
      • Mixed Radix FFT IP Core for Xilinx FPGAs
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      • FFT_PIPE IP Core for Xilinx FPGAs
    • 2D FFT
    • Other IP Cores >
      • Floating Point IP >
        • FPLIC Riviera Evaluation
        • FPLIC Download
        • FPLIC ParaCore Parameters
      • AES Crypto IP >
        • AES PatraCore Parameters
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    • FFT/IFFT ParaCore Parameters
  • Ingenuity
    • ParaCore Architect IP Generation >
      • PCA Flow
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    • Modeling
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    • Fixed vs. Floating Point
    • Fixed Point Math
  • News
    • DE Releases Mixed Radix FFT IP Cores for Xilinx FPGAs
    • DE Release UltraLong FFT IP Cores for Xilinx FPGAs
    • DE Releases FFT_PIPE IP Cores for Xilinx FPGAs
    • Floating Point Modules Evaluation Available
    • Chip Design Magazine Article
    • BCD Math
    • UltraLong FFT IP Success
    • DE Releases FFT IP Cores
  • Docs
    • HowTo >
      • Power Calculation Using XPower
      • Strings in Verilog
      • Inferring Block RAM vs. Distributed RAM in XST and Precision
      • Verilog RTL Coding Style Guidelines, Tips and Template
    • Downloads >
      • gen_ise-sh
      • gen-ise-sh-py
      • deModel
      • deModel_tar_gz
      • deModel_win32_exe
    • HPEC Presentations >
      • HPEC 2003 Presentation
      • HPEC 2004 Presentation
      • HPEC 2007 Abstract
      • HPEC 2007 Posters
    • FFT >
      • Load Unload FFT IP Datasheet
      • FFT_MIXED Candidate Core Datasheet
      • DE FFT IP and Sundance SMT702 Flyer
      • UltraLong FFT IP Core for Xilinx Datasheet
      • PIPE_FFT for Xilinx FPGAs Datasheet
      • FFT Datasheet
      • Floating Point FFT Factsheet
      • FFT Success
    • Sundance DE Partnership Release
    • FPGA Webcast
    • FPGAs Go, Go, Go
    • AES Datasheet
    • FPLIC Specification
    • DE Overview

Careers


Dillon Engineering (DE) is a growing consulting firm delivering excellent engineering solutions to clients ranging from small start-ups to Fortune 500 companies. In order to continue to provide these solutions and add to our capabilities, DE seeks the brightest and most motivated engineers available.

The state-of-the-art projects we are involved in offer a steady stream of new technologies to learn and apply, so anyone joining our team can expect challenging and rewarding project experiences.

Engineers at DE can expect to spend almost 100% of their time doing real engineering work. The average project duration is two to three months with client satisfaction the utmost concern.

While each day is a challenge to stretch your abilities to satisfy our clients, the work environment is family centered and fun. If you look closely you will see many toys tucked away to help entertain the kids when they often stop by.

Rewards include exceptional compensation for exceptional performance. Our competitive benefits include health insurance with company sponsored medical savings account, tax deferred savings plan (with company match up to 3%), health club membership, and flexible work environment.

If you are experienced in DSP and image processing algorithms, FPGA, ASIC, and/or SoC designs, Verilog and/or VHDL and/or C/C++, simulation and synthesis… and if you are interested in working with a dynamic team on cutting-edge technology, check the current openings below:

Current Openings

There are presently no openings at Dillon Engineering.
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