Power calculation using XPower
General Procedure for calculating Power usage in any design
There are two ways to achieve this. The first is a theoritical approach while the second is more based on advanced estimation techniques.
Theoritical Approach
Estimation Approach
Theoritical Approach
- Synthesize the design and obtain the final ncd, pcf and verilog or vhdl gate level design file after making sure all the constraints have been met.
- Compile the gate level design file and the testbench.
- Initialize the simulation
- Trace all the ports and nets in the design to an asdb file.
- Run simulation till the end.
- Convert the asdb file to vcd format using asdb2vcd command
- Start the XPower tool and use the ncd and pcf files created during synthesis and the vcd file generated by the asdb2vcd command.
- If all the steps were executed without errors, the XPower tool would produce the power estimate with a reasonable confidence level.
Estimation Approach
- Synthesize the design and obtain the final ncd and pcf files after making sure all the constraints have been met.
- Start the XPower tool and in a project, pull the ncd and pcf files.
- In the data views window, you would see the separate components of the design that contribute towards the power used, i.e., Clocks, Inputs, Outputs, Signals and Logic.
- The frequency of operation and activity rate of various above mentioned units can be set. The Power estimate is available with a reasonable confidence level after this.
Power Calculation for Large Designs
Power calculation can be a bit tricky especially considering limited available resources either in time or in computer memory or both. XPower needs activity information on each of the ports and nets inside the design for accurate power estimation. Most of this information can be obtained from a vcd file that can be generated from a gate level simulation on any simulator.
Gate level designs often have innumerous nets forming connections between umpteen modules. A full gate level simulation takes a long time to complete if all of these nets are traced into the simulation database. A conversion of these traces into vcd entities would be very taxing on the computer resources and more often than not wasteful.
A few things could be done to make this process quick and effortless. Since the estimate of the power is calculated on the activity recorded on the signals in the time specified, we need to get an estimate of the activity once all the nets and signals are active. An ideal way to do this is to have a number of sets of input data fed into the design continuously but trace all the nets and ports only when the first set of outputs start exiting the design. This would save considerable time during the simulation phase and more time at the actual conversion to vcd entities.
Most deterministic signals would leave some of the nets at constant values. This might be construed as no activity. Input signals have to be chosen so that nets are not at a constant value for long time. Care has to be taken to have sufficient activity on the MSB pins as well. A good way to achieve this is to have random data in the range [-ve maximum value, +ve Maximum value] for all the sets. It would be preferable to have different sets of inputs each time.
Gate level designs often have innumerous nets forming connections between umpteen modules. A full gate level simulation takes a long time to complete if all of these nets are traced into the simulation database. A conversion of these traces into vcd entities would be very taxing on the computer resources and more often than not wasteful.
A few things could be done to make this process quick and effortless. Since the estimate of the power is calculated on the activity recorded on the signals in the time specified, we need to get an estimate of the activity once all the nets and signals are active. An ideal way to do this is to have a number of sets of input data fed into the design continuously but trace all the nets and ports only when the first set of outputs start exiting the design. This would save considerable time during the simulation phase and more time at the actual conversion to vcd entities.
Most deterministic signals would leave some of the nets at constant values. This might be construed as no activity. Input signals have to be chosen so that nets are not at a constant value for long time. Care has to be taken to have sufficient activity on the MSB pins as well. A good way to achieve this is to have random data in the range [-ve maximum value, +ve Maximum value] for all the sets. It would be preferable to have different sets of inputs each time.
