PCA Flow
Generate a ParaCore Virtual Prototype
The first step in the ParaCore Architect™ design flow is for Dillon Engineering to take the client’s algorithmic requirements and return a corresponding mathematical model in ParaCore Architect’s modeling language. This self-executing, bit-accurate, non-implementation-specific model performs the role of a “virtual prototype”:
The virtual prototype is then used to ensure that the algorithms have been captured correctly by inputting algorithmic test data supplied by the client and verifying that the output is correct. Once the client signs-off on the virtual prototype, this will become the “gold standard” against which future ParaCore implementation-level models are compared.
Generate a ParaCore Implementation Model
A ParaCore implementation model starts off as a copy of its associated ParaCore virtual prototype. The designer then starts to specify parameters that target the implementation model towards a target architecture. These parameters will refine such attributes as resource sharing, loop unraveling, pipelining, etc. At every stage, the designer can quickly verify the implementation model against the virtual prototype to ensure functional equivalency.
Generate a VHDL or Verilog Model
Eventually, the ParaCore implementation model will be processed by ParaCore Architect to generate simulatable and synthesizable RTL (VHDL and/or Verilog):
This RTL will be functionally verified using conventional simulation techniques. The RTL will then be synthesized and placed/routed into the target device, followed by timing simulation and verification.
ParaCore Architect Benefits
It provides ultra-fast access to a proof-of-concept (the virtual prototype) that is used to test the algorithms and implement the functionality of the design prior to logic design. This allows designers to resolve design issues as early as possible in the design cycle, and provides a “gold model” against which implementation-specific models can be compared.
It comes equipped with an associated library of proven parametric functions that can be used as building blocks. It results in the creation of a parametric and scalable IP core that can be quickly adapted to meet evolving design specifications it provides tight links to simulation and synthesis. It provides automatic HDL and testbench generation.
It comes equipped with an associated library of proven parametric functions that can be used as building blocks. It results in the creation of a parametric and scalable IP core that can be quickly adapted to meet evolving design specifications it provides tight links to simulation and synthesis. It provides automatic HDL and testbench generation.
