FFT IP cores and DSP design for FPGAs and ASICs#
Dillon Engineering, since 1989
High-performance FFT IP and custom DSP implementation for engineers who need their algorithms running in hardware. Parameterized cores, bit-accurate models, and a design team that speaks your language.
FFT IP cores#
64 to 65,536-point FFT/IFFT at a continuous 275 MSPS with up to 75% frame overlap, on AMD UltraScale+.
Windowed IEEE-754 single-precision FFT/IFFT, 64 to 32K points with up to 50% overlap and any window shape, on AMD UltraScale+.
Pipelined streaming FFT for continuous data at the full clock rate.
Mixed-radix architecture for non-power-of-2 transform lengths.
Very large transforms using external memory.
IEEE-754 floating point throughout, with no fixed-point scaling analysis.
See the side-by-side comparison.
Design services#
Your algorithm, implemented and verified in digital logic.
Our in-house tool for highly parameterized IP generation.
Radar, sonar, communications, imaging and scientific computing.
Latest news#
2026-10-28 Dillon Engineering announces fft_float, a floating-point windowed FFT IP core for UltraScale+ FPGAs
2026-10-23 Dillon Engineering announces 64K-point overlapped FFT IP core for UltraScale+ FPGAs