FFT_PIPE: pipelined FFT#

A pipelined radix-2 FFT for continuous data streams. Each rank has a single butterfly and a single delay-feedback path, which keeps local memory small while sustaining one sample per clock.

Specifications#

Parameter

Value

Architecture

Pipelined radix-2, single butterfly per rank

Data format

IEEE-754 floating point; fixed point of any width

Transform lengths

Run-time selectable, 32 to 64K points (legacy figure)

Throughput

Continuous streaming at Fmax

Deliverables

Netlist or parameterized source; C/C++ bit-accurate model; Verilog testbench

Datasheet status

Legacy (2008)

Architecture#

The core frames incoming data, reorders it for the FFT engine, and passes it through a chain of pipelined ranks. Each rank holds its butterfly math, twiddle-factor ROM and local datapath memory. A length-select stage taps the rank outputs, so the transform length can change at run time.

Start-up latency for a length \(N = 2^m\) is approximately

\[ L \approx 2 \cdot 2^m + m\,(2\,t_{\text{add}} + t_{\text{mult}}) \]

clock cycles, where \(t_{\text{add}}\) and \(t_{\text{mult}}\) are the adder and multiplier pipeline delays.

Customization#

  • Fixed single length or fixed direction for a small logic saving

  • Bit-reversal stage removed (bit-reversed input order)

  • Decimation-in-frequency build option

  • Any floating-point precision, or fixed point of any width with selectable scaling, rounding and saturation

Documentation#